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As shown, lane 0 registers start at 0x400 The following table shows the fht pma lane number to offset address mapping. Base_addr_core + 0x040 register name
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7:0 {lane enable bits} address Lane offset address information is the offset for each lane in the fht and fgt pma register maps Base_addr_core + 0x044 register name
I tried to set brick_config.lane_swizzle to 0x15 (value that should swap lanes to right order) in the csi5_stream_set_config.
Ctrl_lane_ena is a lane enable register, bit 0 is used to enable/disable lane 0, bit 1 is used to enable or disable lane 1, etc For example, lane 0 is disabled if bit 0 is set to 0. After installing the vivado design suite and the required ip service packs, choose a licensing option The simulation only evaluation license key is provided with the xilinx vivado design suite.
For example, you can set 4 lanes in the ip core gui, and then enable or diable the lane as per your needs using the register ctrl_lane_ena Take a looka at pg242 for more info. This is a sample program to control the ena over lan using microsoft excel on an external pc The sample program is written in microsoft excel vba and using winsock api in the windows environment.
You are right not just set the phy_mode also need set the brick_config.lane_polarity [i] for it
2907 //coverity[cert_int30_c_violation] #see phy_brick_reg_offset definition 2930 = ((i >> 1u) == nvcsi_cil_a) 2931 //coverity[cert_int30_c_violation] #see phy_brick_reg_offset definition.
